A semiconductor integrated circuit device usually has plurality of insulating layers and a plurality of wiring layers build up alternatingly on a semiconductor integrated circuit chip. The wiring layers are interconnected by vias, and a plurality of power pads and a plurality of signal pads are disposed on the uppermost wiring layer among the wiring layers. The IC chip has an internal circuit or circuits placed in an internal area, and a plurality of I/O cells (I/O buffers) disposed peripheral to or in close proximity thereto. The internal circuits are electrically connected to corresponding I/O cells through wiring, and the I/O cells are electrically connected to the signal pads and power pads through wiring. The signal pads and power pads are electrically connected to the exterior of the IC chip.
In such a semiconductor integrated circuit device disclosed heretofore, a single power pad (PVDD, PGND) and a plurality of I/O cells disposed on an IC chip are connected by respective ones of a plurality of independent wiring traces (H2, HD, H1) of identical thickness, the plurality of I/O cells are connected to corresponding signal pads (PSIG) by respective ones of independent wiring traces (HS), and the signal pads (PSIG) are arrayed in the area between the power pad and the plurality of I/O cells (see FIG. 6, Patent Document 1). Such an arrangement has the advantage of high packing density and enables the degree of freedom of layout design to be raised without the formation of thick power wiring.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2005-93575A (FIG. 3)